1. Technical Field
The present disclosure relates to a parity error detecting circuit, and more particularly, to a parity error detecting circuit which reduces a latency generated during parity error detection and a method of detecting parity error.
2. Discussion of the Related Art
A data signal transmitted from a transmission terminal may be distorted by noise before being received by a reception terminal. The data signal may be transmitted using a parity bit to ensure that the data signal has been properly transmitted. A parity error detecting circuit may then be used to evaluate the data signal to determine whether the signal has been received without distortion.
FIG. 1 is a block diagram of a conventional parallel parity error detecting circuit 100. FIG. 2 is a timing diagram of the conventional parallel parity error detecting circuit 100 shown in FIG. 1. Referring to FIGS. 1 and 2, the conventional parallel parity error detecting circuit 100 includes a data transformation unit 110, a logic operation unit 120, and a flipflop 130.
The data transformation unit 110 samples a received serial data signal SDATA in response to a first clock signal DCLK, and transforms the sampled serial data signal into parallel data signals Pre_Data<N:0>, where N is a natural number.
The data transformation unit 110 outputs the parallel data signals Pre_Data<N:0> simultaneously in response to a second clock signal CLK.
The logic operation unit 120 includes a plurality of exclusive OR (XOR) gates connected to one another in parallel, and performs XOR operations on the received parallel data signals Pre_Data<N:0> in stages, and outputs the result of the XOR operations. The flipflop 130 receives the result of the XOR operations output by the logic operation unit 120 and outputs the same in response to the second clock signal CLK.
As illustrated in the timing diagram of FIG. 2, the conventional parity error detecting circuit 100 requires the second clock signal CLK to transform the serial data signal into the parallel data signals and to perform logic operations on the parities of the parallel data signals to output the results of the logic operations.
As illustrated in FIG. 1, the number of logic circuits (e.g., XOR circuits) of the logic operation unit 120, that are required for calculating the parities of the parallel data signals, increases according to the number of bits of the received serial data signal. The logic circuits accordingly introduce a propagation delay. Thus, there is a need for a parity error detecting circuit and/or method which reduces a latency generated during parity error detection of the received serial data signal.
FIG. 3 is a circuit diagram of a conventional serial parity error detecting circuit 200. FIG. 4 is a timing diagram of the conventional serial parity error detecting circuit 200 shown in FIG. 3. Referring to FIGS. 3 and 4, the general serial parity error detecting circuit 200 includes an XOR gate 210, a first flipflop 220, and a second flipflop 230.
The XOR gate 210 receives a serial data signal SDATA and a feedback signal Qn, performs an XOR operation on the serial data signal SDATA and the feedback signal Qn, and outputs the result of the XOR operation. The first flipflop 220 outputs the output signal of the XOR gate 210 in response to a first clock signal DCLK. The output signal may be output in response to a rising edge of the first clock signal DCLK. The second flipflop 230 receives the output signal Qn of the first flipflop 220 and outputs the same as a parity error detection signal in response to a second clock signal CLK.
The first clock signal DCLK may be obtained by dividing the second clock signal CLK by N, where N denotes a natural number. The first clock signal DCLK has a period of 1 unit interval (UI). The period of the second clock signal CLK is the same as that of the serial data signal, e.g., a data stream. Each data stream may be composed of N bits, for example, 8 bits. One UI may be one bit of the data stream.
When the serial parity error detecting circuit 200 receives a serial data signal corresponding to one period, checks the parity of the received serial data signal, and outputs the result, the information stored in the first flipflop 220 needs to be initialized to check the parity of a next received serial data signal corresponding to one period. Referring to the timing diagram of FIG. 4, a reset signal RESET of the first flipflop 220 must be enabled during half of one period (i.e., 0.5 UI) of the first clock signal DCLK.
However, when a unit bit of serial data is transmitted at a very high speed, for example, at 2 ns, it may be very difficult to perform a reset operation within 0.5 UI (idea 1 ns). Moreover, an additional device for generating the reset signal RESET is needed. Thus, there is a need for a parity error detecting circuit that does not require reset signals RESET.